DesignCon 2007 Serial Protocol Compliance of an FPGA-Integrated Mixed-Signal Transceiver

The system-level protocol verification of a high-end FPGA with an embedded high-speed serial interface (HSSI) poses challenges that are comparable to and arguably exceed those encountered in ASIC-like verification flows. A single high-end FPGA device with embedded transceivers is designed to provide dedicated hard intellectual property (IP) support for a wide range of industry protocols and applications requiring high-speed serial I/O. This necessitates an efficient verification strategy that deviates from the traditional ASIC flow, leveraging the common aspects of serial protocols while addressing their nuances and maximizing reuse of verification IP in the various stages of the validation flow to achieve time to market with fully functional silicon. This paper describes a strategy devised and successfully utilized for the preand post-silicon protocol verification of an embedded 622-Mbps–6.375-Gbps serial interface in an FPGA. The strategy’s evolution into the validation flow for next-generation protocols such as PCI Express Gen 2 is also discussed. Author Biography Divya Vijayaraghavan is a Senior Member of Technical Staff at Altera Corporation, specializing in developing serial I/O interfaces. She has 11 years of experience in chip design and verification. Divya received her MS degree in electrical engineering from the University of Texas, Austin and her BTech degree in electrical engineering from the Indian Institute of Technology, Madras. She represents Altera on industry standards committees. Introduction The embedded 622-Mbps–6.375-Gbps HSSI referred to in this paper utilized a common physical coding sub-layer (PCS) and physical media attachment (PMA) in hard IP to address the wide range of serial protocols and applications shown in Figure 1. Figure 1. HSSI Serial Protocol Support The high degree of configurability inherent in the hard IP, coupled with a modular architecture and the capability to enable or disable functionality as required, provided the customization required for each protocol and end application. Figures 2, 3, and 4 show simplified depictions of the HSSI configured in PCI Express/PIPE, Gigabit Ethernet, and XAUI modes. A traditional verification methodology would utilize various distinct dedicated verification environments aimed at achieving the degree of functional coverage mandated by each serial protocol and configuration mode in the HSSI, which would naturally be detrimental to the time-to-market requirements of the device. An alternate, more efficient, verification strategy was therefore formulated that emphasized resource sharing and reuse throughout the verification cycle, while retaining the flexibility to cater to defining characteristics of each protocol.